Herein, several related art documents are listed. This list is not an admission that it would be obvious to combine these documents. This list was only compiled post hoc, after the invention described herein was made.
The following document relates to a type of speculation known as “hardware TLS”: Steffan, J. G. 2003 “Hardware Support for Thread-Level Speculation,” Doctoral Thesis. UMI Order Number: AAI3159472, Carnegie Mellon University.
The following document relates to a type of speculation known as “Hardware TM:”
Hammond, L., Wong, V., Chen, M., Carlstrom, B. D., Davis, J. D., Hertzberg, B., Prabhu, M. K., Wijaya, H., Kozyrakis, C., and Olukotun, K. 2004. “Transactional Memory Coherence and Consistency,” In Proceedings of the 31st Annual International Symposium on Computer Architecture (München, Germany, Jun. 19-23, 2004). International Symposium on Computer Architecture. IEEE Computer Society, Washington, D.C., 102. URL=http://portal.acm.org/citation.cfm!id=998680.1006711
The following document relates to IDs used for ordering, the IDs being called “timestamps” in this paper:
Renau, J., Tuck, J., Liu, W., Ceze, L., Strauss, K., and Torrellas, J. 2005. “Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation,” In Proceedings of the 19th Annual International Conference on Supercomputing (Cambridge, Mass., Jun. 20-22, 2005). ICS '05. ACM, New York, N.Y., 179-188. DOI=http://doi.acm.org/10.1145/1088149.1088173
The present invention arose in the context of the IBM® BlueGene® multiprocessor environment. This prior environment had some support for speculative execution, but also some limitations on modes of speculative execution. This multiprocessor environment uses an instruction set in accordance with: IBM® Power ISA™ Version